Ceremorphic AI hardware combines knowledge across many domains, including AI, compilers, computer architecture, analog circuits, and memories. A key component of our system is the high-speed interconnect. The SERDES Senior/Staff Designer would be in charge of a core part of the high-speed PHY, including PCIe, Ethernet, and USB, in advanced FinFet technology nodes. A strong understanding of analog/mixed-signal circuit theories, and expert hands-on design skills, are keys to a successful candidate for this position. Key requirements: -Strong understanding of analog/mixed-signal design theories and practical concepts such as mismatch, ratio-metric, linearity, stability, noise, and low-power -Strong understanding of one of the following core components of a high-speed PHY: CDR, PLL, PI, CTLE, TX Driver, Serializer/De-Serializer -Experience in circuit tradeoff analysis and ability to comprehend system-level specs and their impacts on circuit design, knowledge of PAM4 systems is a plus. -Understanding of the physical layout requirements and hands-on ability to perform critical layouts, experience in FinFet a plus -Proven track record of successful tape out and silicon meeting performance and power specifications, and experience in chip debug/validation/characterization. -The ability to communicate technical issues and present technical reviews coherently and logically are essential. Required Qualifications: 3+ years of experience in analog/mixed-signal IC design Bachelor’s or Master’s degree in Electrical Engineering or related field